Brandon,
I stand mildly correction, section of the 3.3.9 of the IPC-610G may be more appropriate as it seems to cover the same conditions, but also includes test coupons in the description.
Regards,
-JJ
________________________________
JEFFREY A. JENKINS
SR. PCB/CAD Designer CID+
L-3 COMMUNICATIONS LINKABIT DIVSION
3033 Science Park Rd.
San Diego, CA 92121
Tel: (858) 552-9832
Fax: (858) 552-9487
[log in to unmask]
-----Original Message-----
From: Jenkins, JJ @ LINKABIT
Sent: Monday, January 12, 2009 11:09 AM
To: '(Designers Council Forum)'; 'Luther, Brandon'
Subject: RE: [DC] Exposed copper in via holes
Brandon,
The spec I would refer to is IPC-a-600G, section 2.5.4 (Plated-through, Voids, finished coating). I use that to determine acceptability of the bare board. Most of my stuff is class 3, sometimes class 2. I've never had any issues with my vias following the IPC guidelines, but that is just me.
I have a number of boards that have soldermask over the vias on the topside(especially if under BGA devices) and open on the bottom (helps with debug or test points). Most of my vendors ask if they can add the "top soldermask over vias" after the finish plating to minimize chemical entrapment, provide proper plating and minimize voids.
From what they are saying, it would appear that the soldermask was not open on both sides when they did the finish plating, which can leave voids and chemical entrapment. Both can lead to long term issues depending on environment.
So to answer your questions,
What are your opinions on exposed CU in the via barrels?
*No voids is optimal, but I spec class 2 or 3 in general and follow the IPC-610 in this regards.
Do you spec exposed cu in the via barrels?
* I call out the earlier in my notes for the board to made in accordance with IPC-610 class X. If in doubt, put down what is in IPC-610 for the appropriate class in your notes or reference that section in your notes for clarification. Something like "Acceptable Voids in Via wall finished coating shall be IAW IPC-610G 2.5.4 class X" or something similar.
Do you spec any type of via hole protection?
* For myself, beyond the finished plating, in general no. I sometimes do via fill, but that is when I do a Via-In-Pad style technology and it will be plated over. I have seen it used to prevent solder from flowing in the via and as a via wall protectant, but it is an additional process step and a cost adder.
I do spec that the minimum wall plating for Cu shall be .001" for both class 2 and 3, but this is for long-term reliability, and safety factor in preparation of taking the designs lead-free (Cu dissolution concerns).
Hope this helps,
-Jeffrey
________________________________________
JEFFREY A. JENKINS, CID+
SR. PCB/CAD Designer
L-3 COMMUNICATIONS -
LINKABIT DIVSION
3033 Science Park Rd.
San Diego, CA 92121
Tel: (858) 552-9832
Fax: (858) 552-9487
[log in to unmask]
________________________________________
From: DesignerCouncil [mailto:[log in to unmask]] On Behalf Of Luther, Brandon
Sent: Monday, January 12, 2009 10:39 AM
To: [log in to unmask]
Subject: [DC] Exposed copper in via holes
Greetings!
We are qualifying a new PCB vendor and when the samples were cross-sectioned, there was exposed copper in some of the via barrels. They said that it was acceptable and due to the solder mask process. We don't fill the vias.
.
What are your opinions on exposed cu in the via barrels?
Do you spec exposed cu in the via barrels?
I haven't found anything in the IPC documents that specify if exposed cu is acceptable in the via barrels.
Do you spec any type of via hole protection?
.
All responses are appreciated!
Best Regards,
Brandon G. Luther C.I.D.
Design Services Manager
Dataram Corp
609.799.0071 x3481
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