IPC 2222 10.1.1 Edge Spacing - sets the requirement for MINIMUM edge spacing for conductors or spacing from non plated thru holes.
It's a formula... .4mm (.016 in.) plus the required minimum voltage spacing requirements... you find those requirements by voltage range in IPC-2221 table 6-1.
Rule of thumb for low voltage lines is about 20 to 25 mils for good laminating and some in there for process tolerances... Some folks go closer... but it can bite you if you aren't careful. Remember tolerances... never, I repeat... never design to the minimums if you want to be successful. :)
William Brooks, CID+
Senior MTS (Contract)
2747 Loker Ave West
Carlsbad, CA 92010-6603
760-930-7212
Fax: 760.918.8332
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-----Original Message-----
From: DesignerCouncil [mailto:[log in to unmask]] On Behalf Of James Jackson
Sent: Monday, June 03, 2013 10:07 AM
To: [log in to unmask]
Subject: [DC] Exposed edge copper - internal planes
Is there an IPC callout for exposed edge copper?
I seem to remember it not being allowed, but cannot locate an actual statement in any of the IPC documentation.
What I am referring to is when you have a negative copper plane (or copper pour) on an internal layer that extends to the edge of the PCB. When it gets fabricated, there would be a small line of internal copper for each of the planes that extend to the edge of the PCB - which could be shorted together, if a metal object were brought into contact with the exposed copper.
Any thoughts?
Regards,
James Jackson
Oztronics
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