---------Included Message----------
>      From: "Ray Humphrey" <[log in to unmask]>
>      Subject: Re: [DC] Blind and Buried Vias

>      We are starting to design with .5mm pitch, .3mm pad CSPs.  This
doesn't
>      leave room on the inner pads for anything except in-pad, micro
vias.  This
>      is especially true for PCBs in the 2 to 6 GHz range.

Whhhoooya!

Hi Ray,

I've been looking into uVias and "vias in pads" for some time now, and
have a question. Working with high speed devices nowadays the engineers
are very concerned with the inductance losses at the devices, and I've
worked on board where the engineer wanted two caps per power pin to cut
down on the inductance loss. Going to uVias and the likes (anything
under the .8mm BGAs), what does your engineer do to account for the
losses since the uVias don't go directly to a power plane? And, with the
line widths required for 2.5Ghz and above, and the dielectric thickness'
needed for 100ohm differential signalling, and the like I can't even get
directly to a GND plane.

Any suggestions?

Mitch
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